1. Field of Invention
The present invention relates to a signal transmitter, and more particularly to a signal encoder and a signal decoder.
2. Related Art
With the popularity of high-speed circuits, signal characteristics of clock jitter and clock skew have drawn much attention from many engineers. As transmission rates are becoming increasingly higher, clocks are arranged more compactly, and cycles become shorter accordingly. Therefore, the clock jitter now exerts a larger influence.
A conventional digital serial transmission system adopts a data-clock transmission mode. The transmission system uses two signal lines, namely a data line for transmitting a data signal, and a clock line for transmitting a clock signal. As the data signal and the clock signal are transmitted separately, the trouble of clock recovery does not exist at the receiving terminal. Thus, a rising edge or falling edge trigger can be directly used to determine whether the data signal transmitted from the data line is logic zero or logic one. When the data signal is greater than a threshold, it is determined to be logic one. Otherwise, it is Otherwise, it is determined to be logic zero. Though this mode realizes the data transmission, with the extending of transmission distance, the above mode of data-clock transmission will be easily interfered by noise, thus making the level of the data signal entirely moving up or down, and leading to errors of data determination at the receiving terminal. For example, if the level of a signal which is logic zero originally moves up and exceeds the threshold of the above determination due to the noise interference, the receiving terminal will determine the signal is logic one, thus leading to data determination errors.
In order to solve the aforementioned problems, a differential transmission mode is adopted in some of current designs. In this mode, two output terminals (data lines) are both data signals (one is a data signal D+, and the other is a data signal D−). That is, when a data of logic one is to be transmitted, the data signal D+ has a level of logic zero, and the data signal D− is a signal with an inverted phase, and when a signal of logic zero is to be transmitted, the data signal D− is an inverted signal of logic one, and the data signal D+ has a level of logic one. When the receiving terminal receives the signals, the voltage difference obtained from the data signal D+ minus the data signal D− is used to determine logic zero or logic one. When the voltage difference is greater than 0, it is determined to be logic zero. Otherwise, it is determined to be logic one. In this manner, the above problem of noise interference can be effectively alleviated. When the transmitted signals are interfered by noise, as the two data lines are arranged in parallel, the two data lines will be interfered simultaneously, so that the levels of the data signals move up or down simultaneously. Therefore, when the receiving terminal receives the data signals, after the data signal D+ minus the data signal D−, the interference signal is subtracted, thus avoiding determination error.
Though the differential transmission mode solves the problem of noise interference, as the receiving terminal does not have clock signals corresponding to the data lines, the receiving terminal has to use the two data lines to perform clock recovery, which requires that the data output from the data output terminal is not always at the low level (logic zero) or high level (logic one) continuously. Otherwise, the clock recovery will have errors, and the data determination will have errors as well. In order to avoid errors of clock recovery, the industry has developed a data signal conversion mechanism. According to this mechanism, an original 4-bit data is transmitted in 5 bits (i.e., 4B5B), or an original 8-bit data is transmitted in 10 bits (i.e., 8B10B), such that three successive signals at the low level or high level are removed from the transmitted data signal, so as to realize correct pulse recovery. However, though this mode solves the problem of clock recovery, the original 4-bit data must be transmitted in 5 bits, and thus the transmission rate is lowered (by 1.25 times).
In addition, referring to FIG. 1, the differential transmission mode described above has another disadvantage. That is, when the data signal is transmitted on the two data lines, as described above, the problem 300 of switching noise will be generated when the data is switched (e.g., from logic one to logic zero), which will degrade the transmission quality.
Therefore, it has become a problem for researchers to provide a signal transmitter that realizes easy clock recovery and prevents the noise interference.